The standardization of many memory subsystem processes allows for interoperability among different device manufacturers. The standardization allows building devices with different architectural designs and different processing technologies which will function according to specified guidelines. Memory devices receive commands from memory controllers over command buses, which are traditionally trained to ensure that the signaling between the devices meets the expected standards. Training can refer to iterative testing of different I/O (input/output) interface parameters to determine settings that result in best accuracy of signaling on the signal lines. With decreasing device geometries, smaller package sizes, increasing channel bandwidth, and increasing signaling frequencies, differences in design can result in variations in how signals are sent and received between a memory controller and memory device. Thus, the significant variation in memory channel layouts makes it unlikely if not impossible for memory device suppliers to guarantee the memory device will operate in its default state without training the command signaling. Chip select (CS) is a signaling standard used to identify a device that should execute a command on the command bus, and can operate as a trigger for the sending and receiving of data and commands. CS training is traditionally executed as part of command bus training. Without proper I/O training, command and data transfers may be unreliable.
Descriptions of certain details and implementations follow, including a description of the figures, which may depict some or all of the embodiments described below, as well as discussing other potential embodiments or implementations of the inventive concepts presented herein.